RISC-V assembly language
| RISC-V assembly language | |
|---|---|
| Filename extension |
.s |
| Developed by | RISC-V Foundation |
| Type of format | Assembly language |
| Open format? | Yes |
| Free format? | Yes |
| Website | riscv |
RISC-V assembly language is a low-level programming language that is used to produce object code for the RISC-V class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware.
Assemblers include GNU Assembler and LLVM.
Keywords
Reserved keywords of RISC-V assembly language.
- add
- addi
- and
- andi
- beq
- bge
- bgeu
- blt
- bltu
- bne
- lb
- lbu
- lh
- lhu
- lw
- or
- ori
- sb
- sh
- sll
- slli
- slt
- slti
- sltiu
- sltu
- sra
- srai
- srl
- srli
- sub
- sw
- xor
- xori
Mnemonics and opcodes
Each instruction in the RISC-V assembly language is represented by a mnemonic which often combines with one or more operands to translate into one or more bytes known as an opcode.
Registers
RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.
Instruction types
RISC-V instructions use variable-length encoding.
Extensions:
- atomic instructions
- single-precision floating-point
- double-precision floating-point
- bit manipulation
- cryptography
- hypervisor
- supervisor
- packed-SIMD instructions
- vector
Floating-point instructions
RISC-V assembly language includes instructions for a floating-point unit (FPU).
SIMD instructions
These largely perform the same operation in parallel on many values.
Program flow
The RISC-V assembly has conditional branch instructions based on comparison: beq (equal), bne (not equal), blt (less than, signed), bltu (less than, unsigned), bge (greater than or equal, signed), and bgeu (greater than or equal, unsigned).
Examples
.section .text
.globl _start
_start:
lui a1, %hi(msg) # load msg(hi)
addi a1, a1, %lo(msg) # load msg(lo)
jalr ra, puts
2: j 2b
.section .rodata
msg:
.string "Hello World\n"
See also
- Assembly language
- RISC-V ecosystem
- RISC-V instruction listings
- CPU design
- List of assemblers
- x86 assembly language
External links
Content Disclaimer
Informasi ini disarikan dari Wikipedia dan disajikan kembali untuk tujuan edukasi. Konten tersedia di bawah lisensi CC BY-SA 3.0. Kami tidak bertanggung jawab atas ketidakakuratan data yang bersumber dari kontribusi publik tersebut.
- The information displayed on this website is sourced in part or in whole from Wikipedia and has been adapted for the purpose of restating it. We strive to provide accurate and relevant information, however:
- There is no guarantee of absolute accuracy. Wikipedia is an open, collaborative project that can be edited by anyone, so information is subject to change.
- It is not intended to constitute professional advice. The content displayed is for informational and educational purposes only. For important decisions (e.g., medical, legal, or financial), please consult a professional.
- Content copyright. Wikipedia is licensed under the Creative Commons Attribution-ShareAlike License (CC BY-SA). This means that content may be reused with appropriate attribution and shared under a similar license.
- Responsible use. Any risk arising from the use of information from this website is entirely the responsibility of the user.