• An integrating ADC is a type of analog-to-digital converter that converts an unknown input voltage into a digital representation through the use of an integrator.
• Integrating analog-to-digital converters (ADCs) provide high resolution analog-to-digital conversions, with good noise rejection. Basically there are 3 types of  Integrating ADCs.

1. Single-Slope Integrating ADC
2. Dual-Slope Integrating ADC
3. Multi-Slope Integrating ADC
   

The simplest form of an integrating ADC is the single-slope architecture In this architecture the input voltage is integrated and the value compared against a known reference value. Major drawback- Accuracy is dependent on the tolerances of the integrator's R and C values. To overcome this matter The Dual-Slope Integrating ADC is introduced

• The analog switch first connects Vin to the integrator
• The integrator starts generating the saw tooth waveform
• The switch position will remain set at Vin during a fixed number of clock cycles
• Analog switch moves its position to allow –Vref to enter the integrator
• –Vref is a negative voltage, the saw tooth waveform goes towards zero, using a number of clock cycles proportional of the Vin value
  

A dual-slope ADC integrates an unknown input voltage (VIN) for a fixed amount of time (TINT), then "de-integrates" (TDEINT) using a known reference voltage (VREF) for a variable amount of time
The key advantage of this architecture over the single-slope is that the final conversion result is insensitive to errors in the component values. That is, any error introduced by a component value during the integrate cycle will be cancelled out during the de-integrate phase.
In equation form:
TDEINT = TINT × (VIN / VREF)
From this equation, we see that the de-integrate time is proportional to the ratio of VIN / VREF

1. Providing an output with greater noise immunity
2. Averages together all the spikes and dips in the signal within the integration period
3. Escapes the calibration drift problem of the single-slope ADC
4. Easy to obtain good resolution

1. Limits to maximum resolution by the accuracy of the comparator and the quality of the integrator's capacitor

1. Low speed

Dual-slope ADCs are used in applications demanding high accuracy.

• DPM (Digital Panel Meter)

• DMM(Digital Multi Meter)

The normal limit for resolution of the dual-slope architecture is based on the speed of the error comparator

Multi-Slope Integrating ADC has a small slew rate, so the error comparator would allow the integrator to go well beyond its trip point by a considerable amount