As part of a more general rewrite/cleanup, I've fixed a couple of statements made about scaling. Specifically:

• CMOS can scale below 16 nm. I attended a presentation in 2003 where researchers showed the results of testing a 6.3 nm channel FET that they'd fabricated. You could see individual atoms in the micrograph, so yes, it'll hit a wall eventually, but the boundary is mushy and farther away than is usually predicted.
• I've seen articles about FETs that used a single-walled carbon nanotube as the gate. This gives a channel length of 1.1 nm. While this is arguably molecular electronics, you can make quantum wires on similar scales out of silicon too (it's just an incredible pain in the tail).
• The real limit we'll hit for both FETs and molecular computing devices of any type is thermal noise. The energy required to alter the state of a device (be it mechanical or electronic) has to be lower than the average kinetic energy of particles (atoms or molecules, mostly) at the operating temperature. This counts as a mushy limit, because you can go below the usual 4x if you're willing to tolerate more noise, and because you can always lower temperature, but it's a limit. At room temperature this gives you a bare-minimum supply voltage of about 100 mV for conventional electronics.
• The lower limit to power for any kind of device is determined by the energy dissipated per state transition. Bare minimum is 0.1 eV (moving a single electron across a 4kT potential). More realistic values will be in the range of 1 eV. This is still quite low (1 eV is 1.6e-19 J), so I changed "nanowatts" back to "picowatts" (you'd have on the order of 10 million device transitions per second at 1 pW in near practical limits).

Lastly, please, *please*, cite your sources. An article without references is assumed to be junk, so find reputable ones and put them in. In particular, more papers about molecular electronics and molecular-scale mechanical systems would be very handy. --Christopher Thomas 21:49, 21 November 2005 (UTC)[reply]